Due to rapid increase of number core on computing and embedded processing on desire processors the memory(Acronym. RAM) is also one of the key sub areas for better usage of resource allocations and speed up the computing time.

So, LPDDR4 come up with double data rates and optimal power utilization with compared to its predecessors DDR technologies. Rockchip Semiconductors would came to use this LPDDR4 in many of their AMR64 SoC like RK3399, and RK3399.

And it becomes a daunting task for many months to bring up this LPDDR4 initialization into Mainline U-Boot bootloader. Now Amarula Solution Engineer make this into reality with the help of Rockchip engineers YouMin Chen, Kever Yang and community members Akash. We appreciate all engineers efforts equally.

Picture of LPDDR4 running in Rockpro64

Here are the git log commit for LPDDR4 support on rk3399 in Mainline U-Boot

e903ae9127 rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi
0ea86991fc rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
02aa874b34 rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi
0408c03180 rockchip: dts: rk3399: Add LPDDR4-100 timings
aad882231d configs: rock-pi-4: Enable LPDDR4 support
c011dab9e7 configs: rockpro64: Enable LPDDR4 support
7dc1241286 ram: rk3399: Add lpddr4 set rate support
8af5289047 ram: rk3399: Add set_rate sdram rk3399 ops
44c8bdcb29 ram: rk3399: Add LPPDDR4-800 timings inc
26de05c6ce ram: rk3399: Add LPPDDR4-400 timings inc
4c47b03c92 clk: rockchip: rk3399: Set 400MHz ddr clock
06f47ba44d clk: rockchip: rk3399: Set 50MHz ddr clock
bba37550c4 rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for pmu
43ace34d74 rockchip: rk3399: syscon: Add pmu support
9f2a1613f2 arm: include: rockchip: Add rk3399 pmu file
9267a6c5d4 ram: rk3399: Add LPPDR4 mr detection
7629878dab ram: rk3399: Handle data training via ops
fccef0b61f ram: rk3399: Simplify data training first argument
6e21011f15 ram: rk3399: Update lpddr4 vref_mode_ac
194ae79dc1 ram: rk3399: Update lpddr4 mode_sel based on io settings
06934a5549 ram: rk3399: Update lpddr4 vref based on io settings
bfc35c92e2 ram: rk3399: Get lpddr4 tsel_rd_en from io settings
46f3edbe9f ram: rk3399: Configure soc odt support
670bbe643b ram: rk3399: Add tsel control clock drive
7d7d8aed24 ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings
1708038b4a ram: rk3399: Add IO settings
951e395b7d ram: rk3399: Don’t disable dfi dram clk for lpddr4, rank 1
378bf0fdd0 ram: rk3399: Configure tsel write ca for lpddr4
f2215e6a42 ram: rk3399: Map chipselect for lpddr4
a697659f70 ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4
3af757e3db ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4
e5f0361156 ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4
8cc1ca42c7 ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
66dded03fb ram: rk3399: Avoid two channel ZQ Cal Start at the same time
b5678fbb7d ram: rk3399: Don’t wait for PLL lock in lpddr4
4625414fd7 ram: rk3399: Move mode_sel assignment
8fcabbb9bc ram: rk3399: Add lpddr4 rank mask for wdql training
9669d29b13 ram: rk3399: Add lpddr4 rank mask for ca training
094eb271af ram: rockchip: Kconfig: Add RK3399 LPDDR4 entry
0916b71824 ram: rk3399: Configure phy IO in ds odt
8840fb44ad ram: rk3399: Add DdrMode
182e0d0c69 ram: rk3399: Add ddrtimingC0
969a6c8593 ram: rk3399: Add ddr version enc macro
f85076ea6b ram: rk3399: Introduce sys_reg3 for more capacity info
af0346781c ram: rk3399: Rename sys_reg with sys_reg2
0b0d45ff5c ram: rk3399: Simply existing dram enc macro
c6a2bb45cc ram: rk3399: Enable sdram debug functions
f3df644797 ram: rk3399: Add rank detection support
5918b0ef5f ram: rk3399: Compute stride for 1 channel a
e09072b6bf ram: rk3399: Compute stride for 2 channels
e329c52d5c ram: rk3399: debug: Add sdram_print_stride
749290a9d1 ram: rockchip: debug: Get the cs capacity
e5f7737879 ram: rockchip: debug: Add sdram_print_ddr_info
ed5e33e799 ram: rockchip: Add debug sdram driver
2d92f2b6e2 debug_uart: Add printdec
d82d6ba866 ram: rockchip: Add initial Kconfig
3de1e042a6 ram: rk3399: Add pctl start support
ccf2fa1556 ram: rk3399: Move pwrup_srefresh_exit to dram_info
45380845fb ram: rk3399: Add phy pctrl reset support
33f3365ec9 ram: rk3399: Use rank mask in wdql data training
cf01d5ef06 ram: rk3399: Use rank mask in ca data training
b7c3a696d9 ram: rk3399: Clear PI_175 interrupts in data training
a7376957ab ram: rk3399: Handle data training return types
78fc8ecdc2 clk: rockchip: rk3399: Fix check patch warnings and checks
200e6273d4 arm: include: rockchip: Add DDR4 enum
c85f7089c6 arm: include: rockchip: Move dramtypes to common header
c5ad1e51b3 ram: rk3399: Move common sdram structures in common header
e2e04a7d32 ram: rk3399: s/rk3399_base_params/sdram_base_params
a5bd9a7693 ram: rockchip: rk3399: Add cap_info structure
729e8f7dd6 ram: rk3399: Order tsel variables
a5b9da4653 ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p
913feb6916 ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n
ae49177ab7 ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p
f0c5406fa4 ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n
5669dc54db ram: rk3399: Handle pctl_cfg return type
d4ab676847 ram: rk3399: s/sdram_params/params
d1c6717711 ram: rk3399: Some trivial code fixes
ea6132b8b2 ram: rk3399: Fix code warnings

We would come back again on full case study of “DRAM/LPDDR4 bringing-up on embedded computing processors” after some time, till that check this blog and come back us for any questions and queries.